Lecture session B1L-A / 9:00am – 10:00am
Digital & Mixed-Circuit Design I: Analog-to-Digital Conversion
Clic here for detailed information (including list of authors and abstrtact, clic on the paper number)
Clic on the title link below to view the video presentations of each papers:
(the links will be live starting June 12, 2020)
9:00am – 5103 Design Methodology and Timing Considerations for Implementing a TDC on a Cyclone V FPGA Target
9:12am – 5122 Digital Calibration of Capacitor Mismatch and Comparison Offset in Split-CDAC SAR ADCs with Redundancy
9:24am – 5132 A Hybrid 4th-Order 4-Bit Continuous-Time ∆Σ Modulator in 65-nm CMOS Technology
9:36am – 5148 OTA-Free MASH Two-Step Incremental ADC Based on Noise Shaping SAR ADCs
9:48am – 5160 Non-Linear Calibration of Pipeline ADCs Using a Histogram-Based Estimation of the Redundant INL
