T1: Power-Aware Testing in the Era of IoT
by Patrick Girard, Université de Montpellier, France.
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T2: Electronic architectures for Deep Learning
by Bertrand Granado, Sorbonne, France.
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T3: Design Techniques for Reliable High Voltage Gate Drivers with Integrated Power Management for Automotive Applications
by Sri Navaneeth Easwaran, Texas Instruments Inc, USA.
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Power-Aware Testing in the Era of IoT
Live session – June 16, 2020, 8:00am – 9:00am (Montréal time zone)
Patrick Girard, Université de Montpellier, France
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— Abstract — Managing power consumption of circuits and systems is one of the most important challenges for the semiconductor industry in the era of IoT. Power management techniques are used today to control the power dissipation during functional operation. Since the application of these techniques has profound implications on manufacturing test, power-aware testing has become indispensable for low-power LSIs and IoT devices. This tutorial provides a comprehensive and practical coverage of power-aware testing. Its first part gives the background and discusses power issues during test. The second part provides comprehensive information on structural and algorithmic solutions for alleviating test-power-related problems. The third part outlines lowpower design techniques and shows how low-power IoT devices can be tested safely without affecting yield and reliability.
— Bio — Patrick GIRARD received a Ph.D. degree in Microelectronics from the University of Montpellier, France, in 1992, and the “Habilitation à Diriger des Recherches” degree from the University of Montpellier, France, in 2003. He is currently Research Director at CNRS (French National Center for Scientific Research) and works in the Microelectronics Department of the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM) – France. Patrick Girard is Director of the International Associated Laboratory « LAFISI » (French-Italian Research Laboratory on Hardware-Software Integrated Systems) created in 2012 by the CNRS and the University of Montpellier, France, with the Politecnico di Torino, Italy. Since 2006, he is deputy director of the French scientific network dedicated to research in the fields of System-on-Chip, Embedded Systems and Connected Objects (SOC2), a network composed of 1400 researchers. From 2010 to 2014, he was head of the Microelectronics Department of the LIRMM, at that time composed of about 100 people. His research interests include all aspects of digital and memory circuit test and reliability, with emphasis on critical constraints such as timing and power. Robust design of neuromorphic circuits, test of approximate circuits, as well as machine learning for fault diagnosis are also part of his new research activities. Patrick Girard is Technical Activities Chair of the Test Technology Technical Council (TTTC) of the IEEE Computer Society. From 2006 to 2010, he was Vice-Chair of the European TTTC (ETTTC) of the IEEE Computer Society. He has served on numerous conference committees including ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design Automation and Test in Europe (DATE), IEEE International Test Conference (ITC), IEEE VLSI Test Symposium (VTS), IEEE European Test Symposium (ETS), IEEE Asian Test Symposium (ATS), IEEE International NEWCAS Conference, etc. He was the founder and Editor-in-Chief of the ASP Journal of Low Power Electronics (JOLPE). He is an Associate Editor of the IEEE Transactions on Emerging Topics in Computing, the IEEE Transactions on Computers and the Journal of Electronic Testing (JETTA – Springer) journals. He was formerly an Associate Editor of the IEEE Transactions on VLSI Systems and IEEE Transactions on CAD of Circuits and Systems. Patrick Girard has been involved in 29 European and national research projects, and has managed industrial research contracts with major companies like Infineon Technologies, Intel, Atmel, ST-Ericsson, STMicroelectronics, etc. Patrick Girard has supervised 39 PhD dissertations, and has published 7 books or book chapters, 75 journal papers, and more than 250 conference and symposium papers. He is co-author of 4 patents. He is a Fellow of the IEEE.
Electronic architectures for Deep Learning
Live session – June 16, 2020, 9:00am – 10:00am (Montréal time zone)
Bertrand Granado, Sorbonne, France.
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— Abstract — Deep Learning is everywhere, and it is viewed as one of the fundamental components of the smart systems of tomorrow. Today, it is relatively simple to program a convolutional or deep neural network in software – there are several frameworks to do this: Pytorch, TensorFlow, Caffee… -, it is more challenging to integrate the corresponding processing inside a simple hardware object such as those of the Internet of things (IoT). But in our daily life, the tendency is for electronic devices to become smarter. For example, the screening of gastrointestinal pathologies with wireless-capsules will integrate Machine Learning algorithms that take charge of the first stage of the diagnosis; automotive vehicles will be totally autonomous and will adapt to their environments by distributing intelligence among several electronic dispositive in the car. Thus, many applications in biomedical, transportation, networking and other fields will benefit from smart objects. The question is how to integrate such powerful method as Deep Learning in the constrained environment of a simple object. The tutorial will provide a detailed overview of the new developments related to the design of electronic architectures for Deep Learning. Specific topics include (a) History of research on Deep Learning Accelerators (b) new constraint: Low-Energy and Form Factor, (c) Algorithm and Hardware Co-Design for Deep Learning, (d) Tools and method to adapt Deep Learning algorithms to an embedded system. Examples of electronic architectures conceived for Deep Learning for biomedical devices and transport will illustrate the tutorial.
— Bio — Prof. Bertrand Granado received the BS degree in Computer Science in 1991, the MS degree in Computer Architecture in 1994, and the PhD degree in Computer Science in 1998, all from the University of Paris-Sud (Orsay, France). He was assistant and then associate professor at University Pierre and Marie Curie (Paris, France), before becoming full professor at the national school of electrical engineering: ENSEA (Cergy – France) from 2007 to 2012, and full professor at Sorbonne University (Paris, France) since then. His main research interests lie in embedded systems for biomedical applications, and reconfigurable and adaptable hardware, also known as morphware. This includes reconfigurable architecture design, embedded system design, codesign, genetic algorithms, neural networks, and algorithm architecture adequacy. His first Deep Learning architecture, named Maharadja, was conceived in 1998 and supports the real-time execution of the historical LeNet network from Yann Lecun. Since then, he has designed with his team several digital architectures for Machine Learning algorithms, taking into account real-time operation and power consumption constraints. These include models such as RBF, SVM, AdaBoost, fuzzy trees, and CNN.
Design Techniques for Reliable High Voltage Gate Drivers with Integrated Power Management for Automotive Applications
Live session – June 16, 2020, 10:00am – 11:00am (Montréal time zone)
Sri Navaneeth Easwaran, Texas Instruments Inc, USA.
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— Abstract — Gate drivers are commonly used in several electronic applications to drive power transistors that deliver high current outputs. For medium range currents ~ 1A to 5A, the State of the Art is to integrate these power MOSFETs along with their gate drivers (including charge pumps or boost converters that supply the gate drivers) whose operating voltage ranges from 5V to 60V. Reliability of these integrated gate drivers and power transistors is a key factor to meet the high quality demands of the Automotive and Industrial applications. In this tutorial, challenges related to the design and reliability of the High Side (HS) drivers, configurable HS and Low Side (LS) drivers is discussed. Exposure of these gate drivers and powerFETs to several short to ground and battery cycles for reliability is discussed. A new Design FMEA (Failure Mode Effect Analysis) flow along with thermal Safe Operating Area (SOA) flow for designing these drivers for fault tolerance is presented. In addition slew rate control, wave shaping techniques, handling Electro Magnetic Interference (EMI) for the gate drivers are discussed that typically drive wide range of inductive loads . Structures for the proof of concept simulated and measured will be presented. This tutorial will be valuable for the design community to carefully design several low noise safety critical circuits for automotive and industrial applications.
— Bio — Dr. –Ing Sri Navaneeth Easwaran was born in Erode, India in 1977. After his Higher Secondary school, he received his Bachelor of Engineering, B.E. Degree (cum laude) in Electronics and Communication Engineering from Bharathidasan University, India in 1998. He worked at SPIC Electronics and STMicroelectronics in India from1998 to 2000. From 2000 he worked for Philips Semiconductors in India, Switzerland and The Netherlands where he designed analog circuits for Mobile Baseband and Power Management Units. While working at Philips Semiconductors, he also received the International M.Sc. degree in Electrical Engineering from the University of Twente, Enschede (Prof. Dr.ir. Bram Nauta’s ICD group), The Netherlands on the design of NMOS LDOs. From 2006 he started his work at Texas Instruments GmbH Freising, Germany and he joined the Technische Elektronik group at Friedrich-Alexander-Universität Erlangen-Nürnberg in January 2010 as an external Ph.D student under the supervision of Prof. Dr. –Ing. Dr. -Ing. habil. Robert Weigel. His research focused on the fault tolerant design of smart power drivers and diagnostic circuits. He received his Dr.-Ing degree from Friedrich-Alexander-Universität Erlangen-Nürnberg in May, 2017. Since September 2010 he is with Texas Instruments Inc, Dallas, Texas USA where he has lead several high voltage System Basis Chips for transceivers, airbag, power steering and braking applications. He has also designed analog high voltage, negative voltage tolerant circuits for automotive ICs. He was elected as the Senior Member of IEEE in 2011, Member Group Technical Staff at Texas Instruments in 2014 and Senior Member Technical Staff in 2019. He has more than 20 granted patents (US and German) in the field of Analog Mixed Signal Design and has 19 IEEE, conference, functional safety related publications. He has offered several tutorials on Automotive design topics at IEEE Conferences. He is a Technical Program Committee member of IEEE- CAS society since 2018.
